A serial communication system 100 generally includes two serial communication devices 102 and 104 connected by a serial communication bus, cable or transmission line 106, as shown in FIG. 1. The serial communication system 100 is usually included in a computer system, a network of computer systems, or other appropriate electronic devices. The serial communication devices 102 and 104 generally have serial transceivers 108 and 110, respectively, that generate, or drive, serial data stream signals back and forth through the transmission line 106.
Clock speeds for commercially available serial transceivers 108 and 110 currently enable serial data transfer rates up to three to four gigabits per second (3-4 Gbps). Such currently commercially available serial transceivers 108 and 110 may be defined according to specifications for serial communication standards, such as SAS (Serial Attached SCSI (Small Computer System Interface)), SATA (Serial ATA (Advanced Technology Attachment)), Gigabit Fibre Channel, Gigabit Ethernet and any other standard data transfer protocol. At this high serial data transfer rate, there is considerable “jitter” caused by intersymbol interference (ISI) in the serial data signals (along with other problems, such as noise in a power supply and wavering of a crystal oscillator), as will be described by the following explanation. The jitter and ISI problems increase as the serial data transfer rates increase.
The serial transceivers 108 and 110 typically “lock” onto, or “recover,” the clock of the serial data stream signals received from each other with a phase locked loop (PLL) that detects an initial stream of alternating logic 1s and 0s in the serial data stream. The PLL effectively locks onto rising and falling edges in the serial data stream in order for the serial transceivers 108 and 110 to identify the bits in the serial data stream. The ISI problems can cause the timing of the rising and falling edges in the serial data stream to move from their ideal locations in time. Such timing variations are referred to as the “jitter” in the signal. If the jitter is large enough, a bit in the serial data stream may be lost, or the PLL may lose the lock on the clock of the serial data stream signals. To ensure that no bits are lost and that the PLL maintains the lock on the clock of the serial data stream signals, the serial communication standards require an 8B10B encoding scheme (whereby eight bits of data are encoded into ten bits) that allows for a run of consecutive bits having the same logic value (either logic high 1, or logic low 0) for no more than five bits. In this manner, the time between rising and falling edges in the serial data stream is held to a maximum, so the timing variations jitter) are minimized, and the PLL can keep the lock on the clock and ensure accurate data reception at the serial transceivers 108 and 110. As long as the timing variations fall within an allowable “budget” for the amount of jitter a transceiver 108 or 110 can tolerate, the transceiver 108 or 110 can operate properly.
The ISI is affected by characteristics of the transmission line 106. These characteristics are represented by a simplified schematic diagram having serial linear resistors 112 and parallel parasitic linear capacitors 114. The resulting resistance and parasitic capacitance of the transmission line 106 increases with a longer transmission line 106. The transmission line 106 also has a characteristic parasitic linear inductance, but the inductance is very minor, so it is not shown in order to simplify the following analysis and explanation of the shortcomings in the prior art. Thus, the analysis is made with respect to a typical RC circuit.
The voltage response (vs. time) of the RC circuit of the transmission line 106 is illustrated by a graph 116 in FIG. 2. The voltage response graph 116 has an exponential curve with an early portion 118 where the slope is changing rapidly and a later portion 120 where the slope is changing slowly as the curve is approaching an asymptote 122. The capacitance of the transmission line 106 is charged in a corresponding manner. Upon changing from a logic high to a logic low, or vice versa, for the 3-4 Gbps data transfer rates and higher, the end of the bit time 124 for the current bit of the serial data stream occurs within the early portion 118 of the graph 116, where the voltage and the charge in the capacitance are changing rapidly. If the logic value does not change for the second bit, the end of the corresponding bit time 126 occurs further along the graph 116, but still within the early portion 118. Similarly, for the third, fourth and fifth bits, if the logic value still doesn't change, the ends of the corresponding bit times 128, 130 and 132, respectively, occur even further along the graph 116, but likely still within the early portion 118, particularly for the higher data transfer rates.
The resulting parasitic capacitive charge in the transmission line 106 is greater when the end of the last bit time 124-132 for consecutive bits of the same logic value is further up the graph 116. When the parasitic capacitive charge becomes greater, however, it then takes longer or requires a greater drive voltage to drive the signal on the transmission line 106 to the opposite logic value, because the parasitic capacitive charge has to be discharged. Thus, when the drive voltage for the first bit of consecutive bits of the same logic value is large enough to quickly drive the first bit to the desired logic value, the subsequent bits merely cause the parasitic capacitive charge to increase, thereby exacerbating the ISI problem. An example of this situation is illustrated by FIGS. 3 and 4.
A graph in FIG. 3 shows a waveform 134 (a differential signal) for an exemplary serial data stream in which all consecutive bits having the same logic value are driven at the same drive voltage. In this example, bits 136 and 138 are logic low, bits 140, 142, 144, 146 and 148 are logic high, bit 150 is logic low, bit 152 is logic high, bits 154, 156, 158 and 160 are logic low, and the last three bits 162, 164 and 166 are logic high. The drive voltage for each bit 136-166 is the same, as indicated by the distance above or below a threshold line 168. The threshold line 168 is ideally in the middle of the “swing” (i.e. the amplitude between the positive and negative maximums) of the waveform 134.
A graph in FIG. 4 shows a voltage response curve 170 for the waveform 134 of the exemplary serial data stream shown in FIG. 3. The voltage response for each group of consecutive bits having the same logic value (bits 136 and 138, bits 140-148, bits 154-160, and bits 162-166) includes an initial “spike” or “ringing” after which the voltage response settles into an “increasing” curve (“increasing” is positively or negatively away from a threshold line 172). The largest number of consecutive same-logic-value bits (five bits 140-148) allows the curve 170 to increase (to point 174) further than the smallest number of same-logic-value consecutive bits (two bits 136 and 138) allows the curve 170 to increase (to point 176). Therefore, the driving of the first bit 150 following the point 174 has more parasitic capacitive charge to overcome than does the driving of the first bit 140 following the point 176.
To reduce the parasitic capacitive charge resulting from multiple consecutive same-logic-value bits, the waveform is shaped with a different voltage emphasis, or “precomp.” FIGS. 5 and 6 illustrate this situation with a waveform 178 (FIG. 5) for another exemplary serial data stream in which bits 180-210 have the same logic values as the bits 136-166 (FIG. 3). However, the bits 180-210 are not driven at the same drive voltage. Instead, the first bit (180, 184, 194, 196, 198 and 206) following an edge transition in the waveform 178 is driven at a higher drive voltage; whereas, the bits (182, 186-192, 200-204, 208 and 210) that consecutively follow previous bits (180, 184, 198 and 206) of the same logic value are driven at a lower “stepped-down” drive voltage. The lower drive voltage occurs at the second bit (182, 186, 200 and 208) of each group of multiple consecutive same-logic-value bits (180-182, 184-192, 198-204 and 206-210).
A voltage response curve 212 is shown in FIG. 6 for the waveform 178 of the exemplary data stream shown in FIG. 5. After the initial “spike” or “ringing,” the voltage response curve 212 settles into an increasing curve, but at a lower level than did the voltage response curve 170 (FIG. 4) relative to a threshold line 214. Therefore, the point 216 to which the largest number of consecutive same-logic-value bits (five bits 184-192) allows the curve 212 to increase is lower than the point 174 (FIG. 4). Thus, the waveform 178 does not cause the parasitic capacitance of the transmission line 106 (FIG. 1) to charge up as high as does the waveform 134 (FIG. 3). As a result, the bits (180, 184, 194, 196, 198 and 206) are driven to their logic value more rapidly and with less ISI and jitter than are the bits (136, 140, 150, 152, 154 and 162; FIG. 3).
This method of setting the emphasis for the waveform 178 has been demonstrated to work effectively for serial data transfer rates up to 3-4 Gbps. However, this method of setting the emphasis has proven much less effective for faster data transfer rates, since the voltage step is generally too large for short groups of same-logic-value bits (e.g. 2 bits) and too little for long groups of same-logic-value bits (e.g. 5 bits), due to a larger relative difference in capacitive charging for faster data transfer rates than for slower data transfer rates.
It is with respect to these and other considerations that the present invention has evolved.